Advanced manufacturing

Semiconductor capacity re-stress

A forward-dated semiconductor capacity stress across assumed fabrication, component, assembly, and production dependencies.

scenario onlyquasi historicalevidence required

Decision question

How do inventory, supplier diversification, and allocation compare under bounded chip-capacity loss?

Context-only public reference; all topology and numeric parameters are explicit model assumptions.

Generated bounds

Lower0.039677

Central0.039677

Upper0.125139

Dimensionless weighted stress under declared assumptions—not a realized-loss estimate.

Artifact identity

Nodes / edges: 5 / 5
Snapshot: 21fc8222f6d20b085469e5a82c816b0d8786d72946d5e5594eeaa7c7936f9aa4
Observability: not cost effective

Context—not numeric evidence

Results from Semiconductor Supply Chain Request for Information

This official/public page motivates the stress question. It does not provide the topology, weights, shock magnitude, intervention effects, or outcome labels.

Open U.S. Department of Commerce

Independent verification

Rebuild the complete evidence chain.

npm run cascadelens -- cases build semiconductor-capacity-restress
npm run cascadelens -- verify content/cases/semiconductor-capacity-restress/riskpack/

Download RiskPack